Generally, when forming metal lines in semiconductor devices it is conventional to sequentially form lower metal lines, contact plugs and upper metal lines such that the lower and the upper metal lines are connected via the contact plugs. For example, U.S. Pat. Nos. 6,130,102 and 5,284,799 disclose a method for forming contact plugs by a dual damascene process, wherein upper metal lines are formed on the contact plugs. In such conventional processes, an overlap ratio between the contact plugs and the upper metal lines or the lower metal lines is greater than zero, thereby making it difficult to apply nanotechnology to the semiconductor device fabrication.